we got our fpga dev board collecting dust (that's a big no-go). time to get something done here ...
FPGA fun, episode 2. Last time ptr_ was able to print some colors on a old VGA screen with the Xilinx Spartan board. We have "FPGA Prototyping by VHDL Examples" that has a lot if interesting examples, including VGA stuff. There's also the OpenBench logic sniffer that has never been used.
who's in? and when ?
- ptr_ (all the time)
boards in use
avnet spartan demo board
- http://www.em.avnet.com/spartan3a-evl /
- For programming this one, check out http://www.nt7s.com/blog/tag/fpga/ and http://code.google.com/p/avs3a/.
altera pluto based board
- had some trouble with usb-to-serial interface (hw-programmer harvesting 12v from serial RS232 ?)
- altera dev env seems a bitch to install
you can testrun your vhdl code using the opensource toolchain 'ghdl' -- this will generate ELF-binaries which happily run on your pc ( but are not usable on actual fpga hardware -- there are no opensource toolchains to synthesize a bitstream)
here's an example (needed tools: ghdl and gtkwave)
a small test-component (a 15 bit linear feedback shift register)
-- cat lfsr.vhdl entity lfsr is port(ck:in bit; rst : in bit; b: out bit); end lfsr; architecture rtl of lfsr is signal lfsr : bit_vector(14 downto 0) :=B"000000000000001"; begin process(ck,rst) begin if rst='1' then lfsr(14 downto 0) <= "000000000000001"; elsif ck = '1' and ck'event then lfsr <= lfsr(13 downto 0) & (lfsr(14) xnor lfsr(0)); b <= lfsr(0); end if; end process; end rtl; <pre> a 'test-bench' which imports our component and generates some test-data sequence <pre> -- cat lfsr_tb.vhdl -- A testbench has no ports. entity lfsr_tb is end lfsr_tb; architecture behav of lfsr_tb is -- Declaration of the component that will be instantiated. component lfsr port (ck : in bit; rst: in bit; b : out bit); end component; -- Specifies which entity is bound with the component. for lfsr_0: lfsr use entity work.lfsr; signal b : bit; signal ck : bit; signal rst : bit; begin -- Component instantiation. lfsr_0: lfsr port map (ck => ck, rst=>rst, b => b); -- This process does the real job. process begin for i in 65535 downto 0 loop -- Check each pattern. wait for 1 ns; ck <= '1'; wait for 5 ns; ck <= '0'; end loop; wait; end process; end behav;
now we can 'synthesize' these vhdl source-files in several steps
- 'analyze' both files:
ghdl -a lfsr.vhdl ghdl -a lfsr_tb.vhdl
- 'emulate' your test-bench unit:
ghdl -e lfsr_tb
- run the simulation and dump the resulting signals to a vcd file (easy to view in gtkwave
open the out_dump.vcd in gtkwave (you may have to drag the signals you want to inspect into the list of signals to view, zoom out a bit etc.)